Built-in parasitic-diode-based charge injection technique enhancing data retention of gain cell DRAM


A gain cell embedded dynamic random access memory (eDRAM) with a noble charge injection technique is presented. The gain memory cell consists of dual-threshold two logic N-type MOSs implemented during a generic triple-well CMOS process. A negative-voltage toggle on the parasitic junction diode fashioned between the pocket p-well and also the cell knowledge node couples up the cell storage voltages. It results in a abundant enhanced retention time in a compact bit space. Moreover, the technique exhibits abundant strong immunity from the write disturbance. Measured results at 85°C from a one hundred ten nm sixty four kbit prototype eDRAM incorporating the proposed technique demonstrate sixty ninep.c enhanced retention time and eighty six% smaller write disturbance loss compared with the conventional one.

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