Thermal-Aware 3D Network-On-Chip (3D NoC) Designs: Routing Algorithms and Thermal Managements


The 3-dimensional Network-on-Chip (3D NoC) has been proposed to unravel the complicated on-chip communication issues in multicore systems by using die stacking technology lately. However, the high integration density of the stacking dies at high operating frequency results in giant power density. Furthermore, the unequal thermal conductance of various logic layers leads the 3D NoC to face a much severer thermal downside than 2D NoC. Those thermal problems might limit the performance gain of 3D integration and cause lower reliability of the 3D NoC styles. To ensure the thermal safety, the 3D NoC systems generally require a higher cooling method, that will be classified into ?technological approaches? and ?algorithmic/architectural approaches.? The technological approaches work efficiently for removal of internal thermal hotspots through further devices but leads to drastically increasing fabrication cost. On the opposite hand, the algorithmic/architectural design approaches aim to use the approaches of intelligent packet information delivery and temperature control to maximise performance below thermal constraints. Compared with technological approaches, they can control the system temperature at much lower additional circuit/device price. In this text, we tend to specialize in the algorithmic/architectural design approaches and review the trendy packet routing algorithms and thermal managements for thermal-aware 3D NoC systems. Firstly, we introduce the thermal challenges of 3D NoC system and review the encountered design challenges. Then, recent developed techniques to handle the thermal challenges of 3D NoC systems are addressed.

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