PROJECT TITLE :
237 Gbit/s unrolled hardware polar decoder
A new design for a polar decoder employing a reduced complexity successive-cancellation (SC) decoding algorithm is presented. This novel totally unrolled, deeply pipelined design is capable of achieving a coded throughput of over 237 Gbit/s for a (1024, 512) polar code implemented employing a field-programmable gate array. This decoder is 2 orders of magnitude faster than state-of-the-art polar decoders.
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