PROJECT TITLE :
System-level assertions: approach for electronic system-level verification
As design of digital systems become additional advanced and more transistors are incorporated into a single chip, design and verification methodologies moves into higher levels. Currently that style at the register transfer level (RTL) has reached its maturity, the main target is shifting to electronic system level (ESL) design tools, languages and methodologies. At the centre of this and perhaps the foremost difficult are verification ways and tools to use for verifying styles at the ESL. This study presents a replacement concept of system-level assertions for ESL verification. It also demonstrates an surroundings for functionally verifying system-level styles using these system-level assertions. The proposed surroundings adapts existing EDA simulation tools, that are mainly used for RTL design and verification, and utilises them for system-level verification. During this setting, designs are modelled in SystemC-transaction level modelling two.zero, and assertions are written in SystemVerilog. Design and verification components are connected along using SystemVerilog Direct Programming Interface mechanism, and designs that are described in SystemC are verified against system-level assertions within the course of SystemVerilog simulation.
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