PROJECT TITLE :
Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme
A brand new design scheme intended to boost the performance of true single-section clocked (TSPC) dual modulus prescalers is presented. Two branches of TSPC D flip-flops are merged to reduce each power and device count. An HSPICE simulation of the proposed theme demonstrates the very best power efficiency and best power-delay product among the referenced styles.
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