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0.0045 mm2 15.8 µW three-stage amplifier driving 10×-wide (0.15–1.5 nF) capacitive loads with >50° phase margin

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PROJECT TITLE :

0.0045 mm2 15.8 µW three-stage amplifier driving 10×-wide (0.15–1.5 nF) capacitive loads with >50° phase margin

ABSTRACT:

A 3-stage amplifier using embedded capacitor-multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the realm efficiency when driving nF-range capacitive masses (CL) is presented. Not like the standard current-buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and space, whereas securing a large gain-bandwidth product. The created left-half-plane zero additionally advantages the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work advantages from the Miller impact to avoid the realm-consuming resistor, and reduces the entailed capacitances while not lowering the parasitic pole position. A multi-path Gm-boosting second stage enhances the effective transconductance and DC gain. With 0.0045 mm2 of space and 15.8 μW of power, the zero.eighteen μm CMOS 3-stage amplifier measures 1.13 MHz unity-gain frequency, zero.forty one V/μs average slew rate and 56.a pair of° PM at 1 nF CL. Stable responses with >50° PM are attained for a ten × range of CL from zero.fifteen to one.5 nF. The achieved figure-of-merit accounting for each die space and power compares favourably with the state of the art.


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0.0045 mm2 15.8 µW three-stage amplifier driving 10×-wide (0.15–1.5 nF) capacitive loads with >50° phase margin - 4.8 out of 5 based on 25 votes

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