Investigation on High-Performance CMOS With p-Ge and n-InGaAs MOSFETs for Logic Applications


CMOS circuits designed using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for prime-performance logic applications. In this paper, we tend to investigate for the primary time the performance of such circuits using in depth device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a 3-stage ring oscillator is obtained for varying ratio of the channel width of the p- and also the n-MOSFETs, respectively (Wp/Wn). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-primarily based CMOS is obtained for In0.75Ga0.twenty five As channel with width ratio (Wp/Wn) of ten: one. Conjointly, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for $D_it$ exceeding 5 × 10 twelve eV−one · cm−two.

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