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Column-level passive sample and column-shared active readout structure for high speed, low power ROIC

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PROJECT TITLE :

Column-level passive sample and column-shared active readout structure for high speed, low power ROIC

ABSTRACT:

A novel odd–even column-level passive sample and column-shared active readout structure is proposed to realise a high speed, low power and low noise readout integrated circuit (ROIC). This structure reduces the number of operational amplifiers (OPAs) in each column and decreases the power consumption of the column capacitive transimpedance amplifier (CTIA) and output buffer. Compared to the traditional design for medium-scale array ROIC, power consumption of a single column is reduced by 80%. A 320 × 320 array ROIC has been designed for indium antimonide (InSb) cooled infrared detector using the novel structure. The chip is fabricated in the 0.35 μm CMOS process. The total power consumption is <55 mW when operating at 200 Hz frame rate with four outputs and the linearity is 99.95%.


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Column-level passive sample and column-shared active readout structure for high speed, low power ROIC - 4.8 out of 5 based on 25 votes

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