In this reported work, a decrease in saturation current with increasing drain voltage in a 30 V asymmetric DEMOSFET biased at medium gate voltage was observed. The change in parasitic junction fieldeffect transistor (JFET) resistance for different gate and drain voltages is used to explain this phenomenon. The JFET resistance is increased with increasing drain voltage, which causes the saturated drain current to decrease and exhibits a negative dynamic output resistance. Careful design of the drift region doping profile can reduce the JFET resistance and relieve the output resistance issue without affecting the breakdown voltage.
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