PROJECT TITLE :
Hybrid scheme for low-power set associative caches
Proposed may be a dual-mode-access cache to reduce power consumption in set associative caches for embedded systems. The proposed scheme introduces a pre-cache buffer to determine a way to access the cache. This can be a buffered twin-mode cache scheme. The proposed cache shows higher prediction rates and lower power consumption than conventional caches, such as the phased cache or the approach-prediction cache. Cacti and Simplescalar simulators are used for these simulations using SPEC200zero benchmark programs. Experimental results show that the proposed cache reduces power consumption by a mean of 19.7% over typical caches.
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