PROJECT TITLE :
Pipelined phase accumulator using sequential FCW loading scheme for DDFSs
Presented may be a low-power tiny-area pipelined part accumulator (PACC) for direct digital frequency synthesisers (DDFSs). To minimise the number of pre-skewing flip-flops, the proposed theme sequentially loads Frequency Management Word (FCW) input data directly to the corresponding unit accumulators while not through series of flip-flops, therefore reducing the power consumption similarly because the chip area compared to previously reported PACCs. A twenty four-bit PACC using the proposed scheme is fabricated in a very zero.13 m CMOS method with built-in phase-to-amplitude mapping circuitry and a D/A converter for measurements of the PACC performance. Experimental results show that the proposed architecture reduces power consumption by twenty one and thirty four compared to CML-primarily based and static CMOS-based mostly standard PACC designs, respectively.
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