Domain wall motion based magnetic adder


Presented is the primary design of a multi-bit magnetic adder (MA) based mostly on domain wall (DW) motion. All the input and output signals are stored in non-volatile DW shift registers rather than CMOS registers. One will flip off safely the logic circuits without information backup and power them on instantly. This new function guarantees to beat completely the rising standby power issue. Moreover, the direct integration of the memory cell in logic circuits reduces greatly the dynamic power dedicated to data moving between logic and memory. An 8-bit MA has been successfully simulated based on a sixty five nm node.

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