PROJECT TITLE :
Tunable floating active inductor with internal offset reduction
Presented is a transistor-level implementation of a floating and tunable CMOS active inductor. It's based mostly on the classical gyrator-C topology and is enhanced by adding an indoor offset reduction mechanism to guarantee functionality conjointly for unbalanced DC conditions. The realised inductance can be programmed for values between 685 μH and 12.4 mH and is meant to be implemented using standard CMOS technology. Its range of operation is from 250 to 750 kHz and therefore the inductor consumption does not exceed two mW.
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