PROJECT TITLE :
Framework for performing rapid evaluation of 3D SoCs
Integrating additional functionality in a smaller type issue with lower power consumption pushes traditional semiconductor technology scaling to its limits. Three-dimensional (3D) chip stacking is touted as the silver bullet technology that can keep Moore??s momentum and fuel the next wave of client electronic merchandise. Introduced may be a framework that allows fast analysis of 3D SoCs with existing physical design tools.
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