PROJECT TITLE :
60 GHz CMOS power amplifier with Psat of 11.4 dBm and PAE of 15.8%
A sixty GHz power amplifier (PA) for a right away-conversion transceiver using normal ninety nm CMOS technology is reported. The PA includes three cascaded common-source stages with inductive load and inter-stage matching. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a two-approach power dividing and combining design. Instead of the realm-consumed Wilkinson power divider and combiner, a miniature low-loss LC power divider and a combiner are used. This in flip results in more Psat and PAE enhancement. Over the 57-64-GHz band of interest, the PA consumes 44.four-mW and achieves an influence gain (Stwenty one) of twelve.04±one dB. At sixty GHz, the PA achieves Psat of eleven.four mW and a most PAE of fifteen.eightpercent. To the authors data, this is the best PAE ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is terribly promising for sixty GHz short-range communication systems.
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