Low-power design technique for decision-feedback equalisation in serial links


A design technique for performing low-power call-feedback equalisation for multi-Gbit/s serial links is presented. The technique systematically reduces the capacitive loading on the timing-essential node inside the feedback loop of the equaliser. Based mostly on the proposed technique, an architecture capable of both equalisation and digitisation of the received data is presented. Power potency of the proposed architecture is analysed and is compared with that of typical analogue and loop-unrolled decision-feedback equalisers. The technique is validated through a signal-of-concept chip fabricated in 65 nm CMOS.

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