Sell Your Projects | My Account | Careers | This email address is being protected from spambots. You need JavaScript enabled to view it. | Call: +91 9573777164

Low-power design technique for decision-feedback equalisation in serial links

1 1 1 1 1 Rating 4.89 (18 Votes)

PROJECT TITLE :

Low-power design technique for decision-feedback equalisation in serial links

ABSTRACT :

A design technique for performing low-power call-feedback equalisation for multi-Gbit/s serial links is presented. The technique systematically reduces the capacitive loading on the timing-essential node inside the feedback loop of the equaliser. Based mostly on the proposed technique, an architecture capable of both equalisation and digitisation of the received data is presented. Power potency of the proposed architecture is analysed and is compared with that of typical analogue and loop-unrolled decision-feedback equalisers. The technique is validated through a signal-of-concept chip fabricated in 65 nm CMOS.


Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here


Low-power design technique for decision-feedback equalisation in serial links - 4.9 out of 5 based on 18 votes

Project EnquiryLatest Ready Available Academic Live Projects in affordable prices

Included complete project review wise documentation with project explanation videos and Much More...