PROJECT TITLE :
Area scaling analysis of CMOS ADCs
Recently, the continuing reduction of analogue-to-digital converter (ADC) power consumption has received a lot of attention in the literature, while it is often assumed that converter area does not scale well anymore. An area scaling analysis based on historical data is performed. It is shown that ADC area scaling has been alive and well across all ADC topologies, and for both matching and noise-limited ADCs.
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