NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors


During this paper, we have a tendency to report the results of consecutive irradiation and negative bias temperature (NBT) stress experiments performed on p-channel power vertical double-subtle metal–oxide semiconductor transistors. The aim is to look at the consequences of a selected reasonably stress in devices previously subjected to the other kind of stress, additionally on assess if doable the behavior of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices results in a more increase of negative threshold voltage shift thanks to further build-of each oxide trapped charge and interface traps. NBT stress effects in previously irradiated devices may, however, rely on gate bias applied during irradiation and on the full dose received: in the cases of low-dose irradiation or irradiation while not gate bias, the subsequent NBT stress looks to steer to more device degradation, whereas within the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress looks to have a positive role since it practically anneals a part of radiation-induced degradation.

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