PROJECT TITLE :
Inverted bit-line sense amplifier with offset-cancellation capability
An inverted bit-line sense amplifier (BLSA) equipped with offset compensation capability for low-power DRAM applications is proposed. The sequential operation of the inverted BLSA permits us to eliminate the sting dummy array in an open bit-line structure ensuing in 1.sevenp.c less total chip area despite of ten% area penalty of the proposed BLSA occupied by extra switches. For 8-Gb DRAM in twenty-nm class technology, the scan failure induced by Vth variability is completely removed because of the offset cancellation. The proposed BLSA maintains the gradual increase of the sensing delay when decreasing the facility offer all the way down to zero.half dozen V, whereas intrinsic read fail prevails below 0.nine V with the conventional one.
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