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A High-Voltage (>600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology

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PROJECT TITLE :

A High-Voltage (>600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology

ABSTRACT:

A high-voltage lateral double-subtle MOSFET with N-island (NIS) and step-doped drift (SDD) region in partial silicon-on-insulator (PSOI) technology is proposed. Within the lateral direction, the SDD region and the NIS on the buried oxide layer (BOX) introduce 2 additional electrical field peaks, which can improve the surface field distribution and breakdown voltage (BV). In the vertical direction, due to the highly doped NIS, a better electric field is induced into the BOX layer, that will achieve a higher vertical BV. As a consequence, the BV is enhanced considerably. Moreover, the NIS with a larger doping concentration can provide a higher current of the proposed device, and so, the ON-resistance ( is reduced. The 2-D simulation results show that the BV of the proposed structure can achieve 680 V, and is reduced by ten.two% and fourteen.seven% compared with the traditional PSOI and buried n-type layer PSOI, respectively.


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A High-Voltage (>600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology - 4.9 out of 5 based on 45 votes

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