PROJECT TITLE :
A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification
A dynamic Verilog-A resistive random access memory (RRAM) compact model, together with cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, however also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental knowledge, including multilayer RRAM. The physical meanings of the numerous model parameters are mentioned. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the look of RRAM devices for the TCAM macro are mentioned within the context of the energy consumption and worst case latency of the memory array.
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