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Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

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PROJECT TITLE :

Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling

ABSTRACT:

This paper investigates the energy reductions possible in commercially obtainable FPGAs configured to support voltage, frequency and logic scalability combined with power gating. Voltage and frequency scaling relies on in-situ detectors that enable the device to detect valid working voltage and frequency pairs at run-time whereas logic scalability is achieved with partial dynamic reconfiguration. The considered devices are FPGA-processor hybrids with freelance power domains fabricated in 28 nm process nodes. The test case is predicated on a variety of operational situations in that the FPGA facet is loaded with a motion estimation core that may be configured with a variable range of execution units. The results demonstrate that voltage scalability reduces power by up to 60 p.c compared with nominal voltage operation at the same frequency. The energy analysis show that the foremost energy efficiency core configuration depends on the performance needs. An occasional performance situation shows that serial computation is a lot of energy efficient than the parallel configuration while the opposite is true when the performance requirements increase. An algorithm is proposed to combine effectively adaptive voltage/logic scaling and power gating within the proposed system and application.


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Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling - 4.9 out of 5 based on 70 votes

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