Diversity in Cybersecurity


Random telegraph noise (RTN) is one of the vital dynamic variation sources in ultrascaled MOSFETs. In this paper, the recently focused ac entice effects of RTN in digital circuits and their impacts on circuit performance are systematically investigated. Rather than trap occupancy likelihood beneath dc bias condition ( $p_rm dc$ ), that is historically used for RTN characterization, ac entice occupancy probability ( $p_rm ac$ ), i.e., the effective proportion of time entice being occupied underneath ac bias condition, is proposed and evaluated analytically to analyze the dynamic trapping/detrapping behavior of RTN. A simulation approach that absolutely integrates the dynamic properties of ac trap effects is presented for correct simulation of RTN in digital circuits. The impacts of RTN on digital circuit performances, e.g., failure chances of SRAM cells and jitters of ring oscillators, are then evaluated by the simulations and verified against predictions based on $p_rm ac$ . The results show that degradations are highly workload dependent which $p_rm ac$ is critical in accurately evaluating the RTN-induced performance degradation and variability. The results are useful for robust and resilient circuit style.

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