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A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks

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PROJECT TITLE :

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks

ABSTRACT:

We tend to report a dc-coupled burst-mode (BM) receiver for optical links during a dynamically reconfigurable network. Through the introduction of interlocking search algorithms, a strong twenty five Gb/s BM operation is achieved with thirty one ns lock time. At the beginning of the burst, the receiver 1st performs input dc current offset calibration in 12.five ns, then achieves phase lock in 18.5 ns, and after that tracks knowledge using a section interpolator (PI) primarily based bang-bang clock and information recovery (CDR). The sensitivity of the receiver is $-10.nine;text dBm$ (average power, $text BER < 10^-12$) at 25 Gb/s, tested with a single mode 1550 nm reference optical transmitter. There isn't any significant sensitivity penalty in the presence of $pm one hundred;text ppm$ frequency offset between the transmitter and therefore the receiver. Measured power efficiency of the receiver at twenty five Gb/s is four.4 pJ/bit. The core of the 32 nm SOI CMOS circuit occupies $200; upmutext m times 300;upmu text m$.


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A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks - 4.7 out of 5 based on 94 votes

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