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Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design

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PROJECT TITLE :

Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design

ABSTRACT:

During this paper, we present a compact model for metal–oxide-primarily based resistive random access memory (RRAM) devices with bipolar switching characteristics. The switching mechanism depends on the dynamics of conductive filament growth/dissolution in the oxide layer. Besides the dc and pulsed – characteristics, the model additionally captures the RRAM retention property and therefore the temperature dynamics. The model parameters and therefore the device variations are calibrated from the experimental data of IMEC HfOx-based RRAM devices. The model has been implemented in Verilog-A, that will be easily adapted into the SPICE simulator for the circuit-level analysis. As case studies, we have a tendency to demonstrate the model’s applications on the programming scheme design of the 1-transistor-one-resistor array, furthermore the design space exploration of the one-selector-1-resistor cross-point array toward megabit-level.


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Compact Modeling of RRAM Devices and Its Applications in 1T1R and 1S1R Array Design - 4.7 out of 5 based on 94 votes

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