PROJECT TITLE :
A Novel Flexible 3-D Heterogeneous Integration Scheme Using Electroless Plating on Chips With Advanced Technology Node
A unique three-D chip-level heterogeneous integration scheme for low price and rapid pilot demonstration is proposed in this paper. The traditional Bumping fabrication is done at wafer level. But, due to the high cost of whole wafer, choosing chips with advanced technology node may be a better different. Therefore, with the difficulties of the bumping method at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a completely unique heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform will be applied to chip-to-chip or chip-to-wafer theme when chips are fabricated from costly advanced technology node.
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