Digitally tuned degeneration resistance to improve linearity of boost factors for analogue equalisers


An analogue equaliser with a completely unique digitally tuned variable degeneration resistance is realised in a very sixty five nm CMOS technology. Implemented with three parallel resistance branches and one serial resistance branch to well match the optimal conductance curve, the proposed variable degeneration resistance is exploited to attain a good boost vary whereas significantly improving the linearity of the tuned boost factors compared with the equaliser with a traditional degeneration resistance structure.

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