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Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region

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PROJECT TITLE :

Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region

ABSTRACT:

A figure of benefit (FOM) for a CMOS system on chip (SoC) is proposed to properly assess completely different CMOS SoCs in the near-threshold voltage ( $V_rm th)$ region, where the provision voltage ( $V_rm DD)$ is slightly on top of $V_rm th$ . When $V_rm DD$ is scaled down to close $V_rm th$ , the drain current becomes greatly sensitive to $V_rm DD$ or $V_rm th$ ; furthermore, the energy exhibits the identical sensitivity as that within the super- $V_rm th$ region. The conventional FOM, the energy-delay product (EDP), is not applicable in the close to- $V_rm th$ region, because the EDP will not consider the sensitivity difference between the energy and therefore the delay. The procedure for establishing an FOM that can appropriately take into account the sensitivity distinction by fitting the characteristics of a transistor is initial introduced. Then, the FOM developed by the proposed procedure is applied to the examples of an inverter chain operating in both the super- $V_rm th$ and close to- $V_rm th$ regions, that verifies that the proposed FOM is acceptable within the near- $V_rm th$ region, whereas the EDP is not.


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Variation-Aware Figure of Merit for Integrated Circuit in Near-Threshold Region - 4.8 out of 5 based on 49 votes

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