New Assessment Methodology Based on Energy–Delay–Yield Cooptimization for Nanoscale CMOS Technology


A replacement technology assessment methodology is proposed to simultaneously evaluate circuit-level energy, delay, and yield beneath realistic device operation theme through Monte Carlo analysis. Given any yield constraints, this new methodology will maximize the circuit energy efficiency without overdesign. It provides a technique to quantify the tradeoff between energy–delay (ED) and yield. The proposed technique is proved to be economical particularly for low power circuit applications compared with ED-only approach. Taking fourteen-nm FinFET design, for example, the impacts of major variation sources are analyzed for different circuit applications, showing a different trend from the ED-only approach. Similarly, the methodology is also extended to incorporate the impacts of reliability issues. A desired design strategy is found to balance the look deserves and circuit reliability. The proposed methodology is helpful for technology assessment and early stage circuit style and planning.

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