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Breakdown Voltage Model and Electrical Characteristics of CMOS Compatible RESURF STI Drain Extended MOS Transistors

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PROJECT TITLE :

Breakdown Voltage Model and Electrical Characteristics of CMOS Compatible RESURF STI Drain Extended MOS Transistors

ABSTRACT:

A CMOS compatible high-voltage shallow trench isolation (STI) drain extended MOS (DEMOS) transistor is fabricated and its electrical characteristics are studied. A local p-well (PW) plate served as a reduced surface field is adopted to enhance the breakdown voltage (BV) by reducing the effective doping concentration of the accumulation region. The conformal-mapping technique is used to guage the BV of this a pair of-D STI DEMOS structure theoretically. A BV model, that relates the BV to the width of the buildup region $x_a$ and the overlap/underlap $O_!p$ between the local PW plate and therefore the STI, comes. The predictions of this model agree terribly well with both the experimental information and the technology pc-aided-design simulations.


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Breakdown Voltage Model and Electrical Characteristics of CMOS Compatible RESURF STI Drain Extended MOS Transistors - 4.7 out of 5 based on 68 votes

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