PROJECT TITLE :
Design of a 22-nm FinFET-Based SRAM With Read Buffer for Near-Threshold Voltage Operation
A near-threshold voltage ( $V_rm th$ ) operation circuit is important for both energy- and performance-constrained applications. The standard half-dozen-T SRAM bit-cell designed for super- $V_rm th$ operation cannot achieve the target SRAM bit-cell margins like the hold stability, scan stability, and write ability margins within the near- $V_rm th$ region. The recently proposed SRAM bit-cell s with scan buffer suffer from the problems of low browse 0 sensing margin and massive scan one sensing time within the near- $V_rm th$ region. This paper proposes a read buffer with adjusted the quantity of fins or $V_rm th$ to resolve the issues within the close to- $V_rm th$ region. This paper additionally proposes a design methodology for pull-up, pull-down, and pass-gate transistors to attain the target hold stability and presents a good write assist circuit to realize the target write ability within the close to- $V_rm th$ region.
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