Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path


This paper presents a high-throughput and ultralow-power asynchronous domino logic pipeline style technique, targeting to latch-free and very fine-grain OR gate-level design. The knowledge paths are composed of a mix of twin-rail and single-rail domino gates. Twin-rail domino gates are limited to construct a stable important knowledge path. Based on this important knowledge path, the handshake circuits are greatly simplified, that offers the pipeline high throughput and low power consumption. Moreover, the stable important information path enables the adoption of single-rail domino gates in the noncritical knowledge ways. This more saves a ton of power by reducing the overhead of logic circuits. An 8 $,times,$ 8 array style multiplier is used for evaluating the proposed pipeline methodology. Compared with a bundled-data asynchronous domino logic pipeline, the proposed pipeline, respectively, saves up to sixty.2percent and 24.five% of energy in the most effective case and also the worst case when processing totally different data patterns.

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