PROJECT TITLE :
Investigation of Temperature Dependence, Device Scalability, and Modeling of Semifloating-Gate Transistor Memory Cell
A semifloating-gate transistor had been proposed and its memory operate has been demonstrated recently. During this paper, we tend to further investigate its temperature dependency, device scalability, and device modeling. The high-temperature behavior is studied by measuring its endurance, retention, and disturbance immunity at eighty five °C. The device scalability down to the fourteen-nm technology node is investigated by simulation. Its macrodevice model for circuit design is additionally developed. Finally, a memory array with the specific peripheral circuits is intended using the device model developed during this paper.
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