PROJECT TITLE :
Threshold Voltage and DIBL Variability Modeling Based on Forward and Reverse Measurements for SRAM and Analog MOSFETs
A physically primarily based variability model is developed to explain threshold voltage ( $V_T$ ) and drain-induced barrier lowering (DIBL) variations, and their correlations for static RAMs (SRAMs) and analog devices fabricated in an exceedingly 32-nm high- $K$ metal-gate technology. Inputs to the model rely on forward (F) and reverse (R) measurement of transistor pair mismatch. The modeling results are validated on SRAMs and analog devices. Asymmetric and symmetric variation elements of $V_T$ and DIBL variability are extracted by the model. Uneven variation may be a major component accountable for the higher $sigma V_T$ mismatch in saturation region compared with linear region, and better DIBL variability.
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