Comprehensive Performance Benchmarking of III-V and Si nMOSFETs (Gate Length = 13 nm) Considering Supply Voltage and OFF-Current


Comprehensive performance benchmarking results for III-V and Si nanowire nMOSFETs (gate length of 13 nm) are reported based on the atomistic full-band ballistic quantum transport simulation including the effects of parasitic resistance and capacitance. After optimizing the source/drain doping for III-V nMOSFETs (to balance source exhaustion versus tunneling leakage), the current, capacitance, and switching delay ( $textit {CV}/I$ ) metrics are compared across InAs, GaAs, and Si devices with different crystal orientations at various supply voltage ( $V_{mathrm {mathbf {DD}}})$ and OFF-current ( $I_{mathrm{{scriptscriptstyle OFF}}})$ targets. III-V nMOSFETs are projected to improve over Si (e.g., up to $sim 50$ % reduction in gate-loaded $textit {CV}/I$ ) for low-power operation (low $V_{mathrm {mathbf {DD}}}$ , low $I_{mathrm{{scriptscriptstyle OFF}}})$ while they lose advantage in the high-performance (high $V_{mathrm {DD}}$ , high $I_{mathrm{{scriptscriptstyle OFF}}}$ target) region. We also provide analytical models for the effects of carrier effective mass and physically explain how the performance comparison of III-V versus Si changes with device scaling.

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