Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets


We have a tendency to investigate a promising tunnel FET configuration having a gate on the source solely, that is simultaneously exhibiting a steeper subthreshold slope and a better on-current than the lateral tunneling configuration with a gate on the channel. Our analysis is performed based mostly on a recently developed two-D quantum–mechanical simulator calculating band-to-band tunneling and as well as quantum confinement (QC). It is shown that the 2 disadvantages of the structure, namely, the sensitivity to gate alignment and the physical oxide thickness, are mitigated by inserting a counter-doped parallel pocket underneath the gate–supply overlap. The pocket additionally considerably reduces the field-induced QC. The findings are illustrated with all-Si and all-Ge gate-on-supply-solely tunnel field-effect transistor simulations.

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