PROJECT TITLE :
A Comparative Study of Gate Structures for 9.4-kV 4H-SiC Normally On Vertical JFETs
This paper reports the event of nine.four-kV 4H-SiC normally on lateral-channel vertical JFETs. The developed JFETs utilize a buried layer to form a lateral conduction channel, shielding the supply from the results of drain bias. Very cheap measured $R_rm on, sp$ was 127 $hboxmOmegacdothboxcm^2$. Measurements indicate that the channel resistivity can be further reduced by channel optimization. The fabricated JFETs exhibit pentode-like $I_D$–$V_rm DS$ characteristics with a high forward direct-current blocking gain of over five hundred. This paper provides a comparative study of gate structures in order to attain the bottom on -state switching losses and to supply stable forward blocking characteristics for a normally on JFET.
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