Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits


This paper analyzes the impacts of single-charged-lure-induced random telegraph noise (RTN) on FinFET devices in tied- and freelance-gate modes, 6T static random access memory (SRAM) cell stability, and several basic logic circuits. The dependence of RTN on lure location, EOT, and temperature is evaluated through three-D atomistic TCAD simulation. It's observed that the charged lure located near the bottom of sidewall (gate) interface and in the center region between the source and drain can lead to the most vital impact. EOT scaling and higher operating temperature improve the immunity to RTN. RTN degradation in independent-gate mode and also the dependence on the location of the trap and bias-dependent current-conduction path are analyzed. We have a tendency to show that the planar BULK device, with larger subthreshold swing ($S.S.$) and comparable entice-induced $V_T$ shift, exhibits less nominal RTN degradation than FinFET for traps placed within the worst position. But, the larger variability and surface conduction characteristic of the planar BULK device result in broader dispersion and larger worst case RTN degradation than the FinFET device with smaller variability and volume conduction. For traps randomly placed across the interface, similar RTN amplitude dispersions are observed for FinFET and planar BULK devices except in the vicinity of distribution tail due to the sturdy interaction between the charged entice and discrete random dopants in planar BULK devices. For 6T FinFET SRAM cell, the SCAN static noise margin of 64 potential mixtures from trapping/detrapping in each cell transistor is examined. Because of reduced carriers with decreasing supply voltage $(V_rm dd)$, the importance of RTN on subthreshold cell stability will increase. Moreover, the leakage and delay of FinFE- inverters, 2-method nand, and 2-to-one multiplexer are investigated using three-D TCAD mixed-mode simulations. The RTN is found to cause $sim$twenty four%–twenty sevenpercent and $sim$13percent–fifteen% variations in leakage and delay at $V_ rm dd = hbox0.4 hboxV$, respectively, for the logic circuits evaluated.

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