PROJECT TITLE :
Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32-nm FinFET Technologies
The variability impact of line edge roughness (LER) on sub-32-nm fin-shaped FET (FinFET) technologies is investigated from both device- and circuit-level views using pc-aided style simulations. Resist-outlined FinFETs exhibit sizeable device performance variation (up to tenp.c fluctuation in threshold voltage and two hundred% in leakage current) when subjected to fin roughness up to 1 nm root-mean-square amplitude. Spacer-defined FinFETs show negligible device performance variation and exhibit quadratic dependence with LER amplitude. For each patterning technologies, the resulting impact on massive-scale digital-circuit performance variation is found to be minimal in terms of the overall delay mean and variation. This is attributed to self-averaging of uncorrelated LER effects between individual devices at intervals the circuits, ensuing in minimal delay impact for digital-circuit design. The impact of LER on leakage power variation is also found to be minimal for all technologies; but, the mean worth will increase by up to fortypercent for 15-nm resist FinFETs. On this basis, the impact of LER on sub-32-nm FinFET device-level variability is solely vital for resist devices, whereas the resulting digital-circuit impact is very important solely in terms of mean leakage power increase.
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