Design Optimization for Digital Circuits Built With Gate-All-Around Silicon Nanowire Transistors


The planning optimization for digital circuits designed with gate-all-around silicon nanowire transistors (SNWTs) is discussed in details. Based on the verified multiwire SNWT compact model with correct parasitic capacitance and resistance modeling, the design consideration of SNWT digital circuits (SNWTCs) at a 16-nm technology node, like the SNWT ring oscillator (SNWT-RO), is discussed with the optimization of key process and layout parameters in the multiwire SNWT. So as to cut back the parasitic elements of SNWTs and improve SNWTCs' performance (as well as delay, power, and layout space), method (together with nanowire diameter and other related parameters) and layout parameters (as well as wire range per transistor and footprint width of SNWTs) ought to be rigorously designed. Through design optimization, the entire capacitance and parasitic resistance of the SNWT will be reduced by over eightypercent compared with nonoptimized parasitic parts, which leads to additional than 90% reduction of circuit-level delay and power. Furthermore, the design optimization is dispensed for power-driven design and area-driven design, respectively. For every case, the SNWT-RO with fan-out of one loading and four loading is optimized with variable power provide voltage for optimization. The optimized layout parameters for power-driven style and space-driven style are obtained, that will give useful tips for SNWTC style.

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