Device Design and Estimated Performance for p-Type Junctionless Transistors on Bulk Germanium Substrates

PROJECT TITLE :

Device Design and Estimated Performance for p-Type Junctionless Transistors on Bulk Germanium Substrates

ABSTRACT :

The junctionless nanowire transistor (JNT) has recently been demonstrated to be a promising device for sub-20-nm nodes. Therefore far, most devices were made on semiconductor-on-insulator substrates. The aim of this work is to evaluate the concept of multigate germanium (Ge) JNTs on bulk substrates, using a dedicated modeling methodology. The variation of device performance due to geometry, channel, and substrate doping concentrations is discussed and proposed as a guideline for planning p-kind Ge bulk JNTs. This work shows that a potential barrier is formed within the substrate by the p-n junction that isolates the channel from the substrate, and an effective confinement of current in the nanowire will be achieved. The Ge bulk JNT facilitates wonderful scalability. Our modeling predicts that, for a gate length of 16 nm, a subthreshold slope of seventy seven mV/dec and a drain-induced barrier lowering of 70 mV will be obtained with an $I_rm on/I_rm off$ current ratio of $hbox1.1 times hbox10^5$.

• Influence of Built-In Drift Fields on the Performance of InP-Based HBTs Grown by Solid-Source MBE
• Effect of Asymmetric Channel on Charging Behavior of 22-nm Quantum-Dot Floating-Gate Flash Memory Cell