Field Plate Optimization in Low-Power High-Gain Source-Gated Transistors


Source-gated transistors (SGTs) have potentially terribly high output impedance and low saturation voltages, that create them ideal as building blocks for high-performance analog circuits fabricated in thin-film technologies. The standard of saturation is greatly influenced by the planning of the sphere-relief structure incorporated into the supply electrode. Beginning from measurements on self-aligned polysilicon structures, we show through numerical simulations how the sphere plate (FP) design will be improved. A simple source FP around one $mu hboxm$ long situated many tens of nanometers above the semiconductor can increase the low-voltage intrinsic gain by a lot of than 2 orders of magnitude and offers adequate tolerance to method variations in a moderately scaled skinny-film SGT.

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