PROJECT TITLE :
Novel Concept of the Three-Dimensional Vertical FG nand Flash Memory Using the Separated-Sidewall Control Gate
Recently, we tend to proposed a novel three-D vertical floating gate (FG)-kind nand Flash memory cell array using the separated-sidewall management gate (CG) (S-SCG). This novel cell consists of one cylindrical FG with line-sort CG and S-SCG structures. For simplifying the method flow, we tend to realized the common S-SCG lines by using the prestacked polysilicon layer, through which variable medium voltages are applied not only to control the electrically inverted S/D region however conjointly to help the program and erase operations. During this paper, we successfully demonstrate the conventional Flash cell operation and show its superior performances in comparison with the recent 3-D FG nand cells by using the cylindrical device simulation. It is shown that the proposed cell can realize the highest CG coupling ratio, low-voltage cell operations of program with 15 V at $V_rm th = hbox4 hboxV$ and erase with fourteen V at $V_rm th = -hbox3 hboxV$, good retention-mode electric field, and sufficient read-mode on-current margin. Moreover, the proposed S-SCG cell array will totally suppress each the interference effects and therefore the disturbance issues at the identical time by removing the direct coupling effects in the same cell string, which are the most important issues of the recent 3-D vertical stacked cell structures. Higher than all, the proposed cell array has good potential for terabit three-D vertical nand Flash cell array with highly reliable multilevel cell operation.
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