PROJECT TITLE :
First Demonstration of Quasi-Planar Segmented-Channel MOSFET Design for Improved Scalability
Quasi-planar segmented-channel MOSFETs (SegFETs) with gate lengths right down to $sim$forty five nm are fabricated employing a typical process flow by beginning with a corrugated-silicon substrate. Compared with control devices (fabricated using the same method flow, but with a planar-silicon substrate), the SegFETs show reduced short-channel result due to enhanced electrostatic integrity. Despite having a smaller physical channel width, the SegFET can achieve comparable drive current per unit layout space as the standard planar MOSFET style.
Did you like this research project?
To get this research project Guidelines, Training and Code... Click Here