PROJECT TITLE :
Reliability Analysis of Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors
In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si skinny-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering impact (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating $hboxn^+$ region have higher immunity to DIBL. Second, VSA-TFTs with a longer floating $hboxn^+$ region additionally have better immunity below hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating $hboxn^+$ region also have higher immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, together with SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating $hboxn^+$ region. Third, the PGB stress, rather than SH stress or HC stress, becomes a significant issue for VSA-TFTs below the stress bias below four V. In other words, PGB stress will dominate the degradation behaviors when the strain bias isn't high enough to attain SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs beneath HC stress, just like that of most TFT devices, happens when the stress of $V_G$ is less than [*fr1] of $V_D$.
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