Performance Evaluation of III–V Nanowire Transistors


III–V nanowire (NW) transistors are an rising technology with the prospect of high performance and low power dissipation. Performance evaluations of those devices, however, have centered mostly on the intrinsic properties of the NW, excluding any parasitic components. During this paper, a III–V NW transistor design is investigated, based on a NW array with a sensible footprint. Based mostly on scaling rules for the structural parameters, three-D representations of the transistor are generated, and also the parasitic capacitances are calculated. An entire optimization of the structure is performed based mostly on the RF performance metrics $f_T$ and $f_max$, using intrinsic transistor information combined with calculated parasitic capacitances and resistances. The result's a roadmap of optimized transistor structures for a group of technology nodes, with gate lengths down to the 10-nm-length scale. For every technology node, the performance is predicted, promising operation in the terahertz regime. The resulting roadmap has implications as a reference each for benchmarking and for device fabrication.

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