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High-Density Large-Area-Array Interconnects Formed by Low-Temperature Cu/Sn–Cu Bonding for Three-Dimensional Integrated Circuits

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PROJECT TITLE :

High-Density Large-Area-Array Interconnects Formed by Low-Temperature Cu/Sn–Cu Bonding for Three-Dimensional Integrated Circuits

ABSTRACT :

High-density area-array three-D interconnects are a key enabling technology for three-D integrated circuits. This paper presents results of the fabrication and testing of large 640 by 512 area arrays of Cu/Sn–Cu interconnects positioned on ten-$muhboxm$ centers. The processes used to create the interconnects are designed to be compatible with CMOS wafer needs. Through testing of the electrical continuity of long chains of interconnects, bond yield is estimated to be greater than ninety nine.99percent in the large arrays. The properties of Cu/Sn–Cu interconnects remain stable through exposure to thermal cycling and high-humidity testing. For applications that have a low thermal budget, bonding of Cu/Sn–Cu at 250 $^circhboxC$ and at 210 $^circhboxC$, below the melting point of Sn, is demonstrated to produce equally high yield and alloy composition as the higher temperature bonds.


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High-Density Large-Area-Array Interconnects Formed by Low-Temperature Cu/Sn–Cu Bonding for Three-Dimensional Integrated Circuits - 4.9 out of 5 based on 71 votes

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