A Physical Model for Grain-Boundary-Induced Threshold Voltage Variation in Polysilicon Thin-Film Transistors


Grain boundaries (GBs) within the channel region of polysilicon skinny-film transistors (poly-Si TFTs) lead to giant variations in the performance of TFTs (delay and power). In this paper, we have a tendency to gift a physical model to characterize the GB-induced transistor threshold voltage variations considering not only the number but additionally the position and orientation of each GB in three-D area. The estimated threshold voltage variations show a smart agreement with experimental knowledge and simulations performed by a numerical three-D drift-diffusion device simulator. Using the proposed model, the impact of GBs on TFTs for various grain sizes, device sizes, and source–drain voltages is mentioned very well. Specifically, when the grain size is resembling the scale of the device, we have a tendency to observed that threshold voltage $(V_rm th)$ variations significantly increase, and $V_rm th$-distributions are non-Gaussian. Finally, using our model, we predict and demonstrate the GB-induced variations beneath completely different crystallization methods, such as sequential lateral solidification.

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