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Gate Bias Stresses of Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels

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PROJECT TITLE :

Gate Bias Stresses of Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels

ABSTRACT :

Gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with multiple nanowire channels has higher performance compared with planar TFT, such as lower threshold voltage $V_rm TH$, smaller subthreshold swing (SS), lower minimum current $I_ rm OFF$, higher maximum on/off current ratio $I_rm ON/I_rm OFF$, and better mobility. But, every nanowire has 3 sharp corners to get high native electric fields below gate bias stresses, such that GAA TFT inherently suffers from an inevitable reliability downside. The native electrical fields accelerate the degradation of $V_rm TH$ and SS. The $V_rm TH$ degradation beneath negative gate bias stress is connected to the released electron trapping in stressed gate oxide during diffusion-controlled electrochemical reaction. For GAA TFT, minimum $I_rm OFF$ and $I_rm ON/I_rm OFF$ ratio still maintain better characteristics thanks to smaller channel body. Moreover, the plain retardation in mobility degradation was obtained for GAA TFT because the hydrogen atoms can effectively rearrange the tail states located close to the band edge within the channel throughout gate bias stresses.


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Gate Bias Stresses of Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels - 4.8 out of 5 based on 49 votes

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