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Edge Effects in Bottom-Gate Inverted Staggered Thin-Film Transistors

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Edge Effects in Bottom-Gate Inverted Staggered Thin-Film Transistors


For thin-film transistor (TFT) characterization and simulation, correct knowledge of the effective channel width ($W_rm EFF$) and effective channel length ( $L_rm EFF$) is required, notably in narrow and/or short devices, where little dimensional variations could lead to massive overestimation/underestimation of device parameters. Though a considerable amount of research has been done to see $L_rm EFF$, there's terribly little work presented regarding $W_rm EFF$. Here, we have a tendency to report a style-related existence of current leakage ways along the channel edges in inverted staggered TFT structures. Applied here for the case of amorphous-silicon- and amorphous-oxide-semiconductor-based TFTs, a model is developed to research the sting impact from a series of TFTs with numerous channel widths ($W$). $W_rm EFF$ is found to be larger than the designed $W$ , ensuing in an overestimation of the extracted TFT parameters like the sphere-result mobility. It is concluded that a most well-liked TFT style consists of supply and drain electrodes that stretch over the active space along the $W$ direction to minimize the sting effects and, hence, improve the accuracy of the extracted TFT parameters.

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Edge Effects in Bottom-Gate Inverted Staggered Thin-Film Transistors - 4.7 out of 5 based on 68 votes

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